The present invention relates to a floorplanning device and a floorplanning method for a semiconductor integrated circuit for determining a placement of blocks based on delays along timing paths between the blocks.
In recent years, LSI designs have been more and more complicated along with the increase in the scale of integrated circuits, as in “system LSIs”, and the miniaturization in the semiconductor process rules.
In the place-and-route phase of the LSI design process, the entire design is in some cases optimized in a “flat” manner or non-hierarchically or, in other cases, the entire design is divided into a plurality of circuit portions called “blocks” and optimized block by block or hierarchically. With the former method, since the entire design is optimized as a whole, a smaller circuit area is more likely to be achieved and the timing convergence is high. However, the process time is longer, and when a change is made to the circuit design, the whole optimization process need to be performed again. With the latter method, processes for different blocks can be run in parallel, thereby shortening the overall process time, and when a change is made to the circuit design, it is not necessary to perform the whole optimization process again. However, the timing convergence between blocks is poor, and the circuit area is likely to be larger.
When designing a system LSI, it is often the case that different design teams work on different blocks, and IPs (Intellectual Properties) are used in many cases in order to increase the design efficiency. In such cases, the hierarchical place-and-route method is more effective.
In the hierarchical place-and-route method, floorplanning for determining the placement of blocks within a chip is performed before more detailed place-and-route process is performed. Floorplanning is very important to improve the timing convergence between blocks and to realize smaller circuit areas. As the feature size is becoming so small that the interconnect delay is no longer negligible, it is becoming common to perform floorplanning as early as in the logic design phase or the RTL (register transfer level) design phase.
The placement of blocks in a floorplan can be determined by referring to the specifications of the LSI, or the blocks can be placed automatically by a floorplanning tool while visually checking the interconnections displayed by the graphic user interface (GUI) of the floorplanning tool.
FIG. 10 shows a flow chart of a conventional floorplanning method in which blocks are placed automatically taking timing into consideration. Based on the interconnect length for the inter-terminal connection in the initial placement (step 1000), the delay along the timing path is calculated in the path delay calculation step (step 1001). The obtained result is evaluated in the convergence determination step (step 1002) based on an evaluation formula for improving portions where a predetermined delay time is exceeded. If the evaluation formula does not converge, blocks are moved around in the placement changing step (step 1003), and the delay calculation is performed again for the new interconnect length after the change of the coordinates of the blocks. This is repeated until the evaluation formula converges.
In another conventional approach, as disclosed in Japanese Laid-Open Patent Publication No. 2000-339364 (page 7, FIG. 2), blocks having a larger number of paths therebetween for which a predetermined delay time is exceeded are placed adjacent to each other preferentially, based on the interconnect length calculated by using statistical interconnect length data without repeatedly performing the placement process and the delay calculation process.
Where the placement is manually determined, it is common to determine the placement while referring to the number of inter-block connections, which is displayed to the user. In another conventional approach, as disclosed in Japanese Laid-Open Patent Publication No. 2000-200835 (page 8, FIG. 2), for example, the direction in which a block is to be moved is determined and displayed to the user by analyzing changes in the interconnect delay while virtually moving the block around.
With a common conventional floorplanning device and method as shown in FIG. 10, the process time is long because it is necessary to repeat the delay calculation every time a block is moved.
With a conventional floorplanning device and method as disclosed in Japanese Laid-Open Patent Publication No. 2000-339364, the inter-block interconnect delay is obtained based on statistical interconnect length data, whereby there may be an error in the actual inter-block interconnect length after the actual place-and-route process. If the inter-block interconnect length, which is significantly dependent on the floorplan, contains an error, the error will degrade the quality of automatic placement.
With a conventional floorplanning device that displays the number of inter-block connections, based on which the user determines which blocks should be placed adjacent to each other preferentially, the displayed information does not include timing-related information, whereby it is difficult to find blocks that need to be adjacent to each other for a timing-related reason from among all the blocks that should be adjacent to each other. Therefore, after the placement is once determined, it is necessary to review the placement based on the results of a timing analysis.
With a conventional floorplanning device and method as disclosed in Japanese Laid-Open Patent Publication No. 2000-200835, the interconnect delay needs to be evaluated every time a block is moved for an improvement, whereby the process time increases in proportion to the number of nets.